--- arch/ppc/mm/init.c

+++ arch/ppc/mm/init.c

@@ -606,9 +606,19 @@ void update_mmu_cache(struct vm_area_str

struct page *page = pfn_to_page(pfn);

if (!PageReserved(page)

&& !test_bit(PG_arch_1, &page->flags)) {

- if (vma->vm_mm == current->active_mm)

+ if (vma->vm_mm == current->active_mm) {

+#ifdef CONFIG_8xx

+ /* On 8xx, cache control instructions (particularly

+ * "dcbst" from flush_dcache_icache) fault as write

+ * operation if there is an unpopulated TLB entry

+ * for the address in question. To workaround that,

+ * we invalidate the TLB here, thus avoiding dcbst

+ * misbehaviour.

+ */

+ _tlbie(address);

+#endif

__flush_dcache_icache((void *) address);

- else

+ } else

flush_dcache_icache_page(page);

set_bit(PG_arch_1, &page->flags);

}